1. Field of the Invention
The present invention relates to a digital video signal record and playback device for recording and playing back a digital video signals and more particularly to a digital video signal record and playback device for recording and playing back on a medium such as an optical disc or the like, a digital video signal coded on the basis of a motion compensation prediction and an orthogonal conversion.
2. Description of Related Art
FIG. 1 is a block circuit diagram of a conventional optical disc record and playback device shown in the Japanese Patent Application Laid-Open No. HEI 4-114369 (1992). Referring to FIG. 1, reference numeral 201 denotes an A/D converter for converting a video signal, an audio signal or the like into digital information. Reference numeral 202 denotes a data compressing circuit, 203 a frame sector converting circuit for converting compressed data into sector data which is equal to integer times of a frame cycle, 204 an error correction coder for adding the error correction signal to sector data, 205 a modulator for modulating interference between codes in a recording medium into a predetermined modulation code to reduce the interference, 206 a laser driving circuit for modulating laser light in accordance with a modulation code, and 207 a laser output switch. Further, reference numeral 208 denotes an optical head for emitting laser light, 209 an actuator for tracking a light beam emitted from the optical head 208, 210 a traverse motor for sending the optical head 208, 211 a disc motor for rotating an optical disc 212, 219 a motor driving circuit, 220 a first control circuit and 221 a second control circuit. Further, reference numeral 213 denotes a playback amplifier for amplifying a playback signal from the optical head 208. Reference numeral 214 denotes a demodulator for obtaining data from a recorded modulation signal, 215 an error correction decoder, 216 a frame sector inverse converting circuit, 217 a data extending circuit for extending the compressed data, 218 a D/A converter for converting extended data into, for example, an analog video signal and an audio signal.
FIG. 2 is a block circuit diagram showing an inside structure of the data compressing circuit 202 in FIG. 1. In FIG. 2, a digital video signal inputted from the A/D converter 201 is inputted into a memory circuit 301. A video signal 321 outputted from the memory circuit 301 is provided as a first input of a subtracter 302 and a second input of a motion compensation predicting circuit 310. An output of the subtracter 302 is inputted to a quantizer 304 via a DCT (discrete cosine transform) circuit 303. An output of the quantizer 304 is provided as an input of a transmission buffer 306 via a variable-length encoder 305. An output of the transmission buffer 306 is outputted to the frame sector converting circuit 203. In the meantime, an output of the quantizer 304 is inputted to the inverse DCT circuit 308 via an inverse quantizer 307. An output of the inverse DCT circuit 308 is provided as a first input of an adder 309. An output 322 of the adder 309 is provided as a first input of a motion compensation predicting circuit 310. An output 323 of the motion compensation predicting circuit 310 is provided as a second input of the adder 309 and a second input of the subtracter 302.
FIG. 3 is a block circuit diagram showing an inside structure of the motion compensation predicting circuit 310 in FIG. 2. In FIG. 3, the output 322 of the adder 309 is provided as an input terminal 401a while the output 321 of the memory circuit 301 is provided as an input terminal 401b. The signal 322 inputted from the input terminal 401a is inputted to a frame memory 404a or a frame memory 404b via a switch 403. A reference picture outputted from the frame memory 404a is provided as a first input of a motion vector detecting circuit 405a. The video signal 321 inputted from the input terminal 40b is inputted to a second input of the motion vector detecting circuit 405a. An output of the motion vector detecting circuit 405a is inputted to a prediction mode selector 406. In the meantime, the reference picture outputted from the frame memory 404b is provided as a first input of a motion vector detecting circuit 40b. The video signal 321 inputted from the input terminal 40b is provided as the second input of the prediction mode selector 406. The video signal 321 inputted from the input terminal 401b is provided as a third input of the prediction mode selector 406. A zero signal is provided as a second input of a switch 407. A second output of the prediction mode selector 406 is provided as a third input of the switch 407. The output 323 of the switch 407 is outputted from a output terminal 402.
FIG. 4 is a block circuit diagram showing an inside structure of the data extending circuit 217 in FIG. 1. In FIG. 4, the video signal inputted from the frame sector inverse converting circuit 216 is inputted to a reception buffer 501. An output from the reception buffer 501 is inputted to a variable-length decoder 502, and the output therefrom is inversely quantized at an inverse quantizer 503. Then, the output is subjected to an inverse discrete cosine transform at an inverse DCT circuit 504. The output is provided as a first input of an adder 506. In the meantime, the output of the reception buffer 501 is provided as a prediction data decoding circuit 505 while an output of the prediction data decoding circuit 505 is provided as a second output of the adder 506. The output of the adder 506 is outputted to the D/A converter 218 via a memory circuit 507.
Next, operation of the device of FIG. 1 will be explained. As one high efficiency coding mode in the case of coding a video signal, there is an coding algorithm for a MPEG (Moving Picture Expert Group) mode. This is a hybrid coding mode which combines an inter-frame prediction coding using a motion compensation prediction and an intra-frame conversion coding. This conventional example uses a data compressing circuit 202 having a structure shown in FIG. 2 and adopts the aforementioned MPEG mode.
FIG. 5 shows a simplified data arrangement structure (layer structure) of MPEG mode. In FIG. 5, reference numeral 621 denotes a sequence layer comprising a group of pictures (hereinafter referred to as “GOP”) comprising a plurality of frame data items, 622 a GOP layer comprising several pictures (screens), a 623 a slice which divides one screen into several blocks, 624 a slice layer which has several macroblocks, 625 a macroblock layer, 626 a block layer which includes 8 pixels×8 pixels.
This macroblock layer 625 is a block which includes a least unit of 8 pixels×8 pixels, for example, in the MPEG mode. This block is a unit for performing DCT. At this time, a total of 6 blocks, including adjacent four Y signal blocks, one Cb block which corresponds to the Y signal blocks in position, and one Cr block are referred to as a macroblock. A plurality of these macroblocks constitute a slice. In addition, the macroblocks constitute a minimum unit of a motion compensation prediction, and a motion vector for the motion compensation prediction is formed in macroblock units.
Subsequently, a process for the inter-frame prediction coding will be explained. FIG. 6 shows an outline of the inter-frame prediction coding. Pictures are divided into three types, namely an intra-frame coded picture (hereinafter referred to as an I picture), a one direction prediction coded picture (hereinafter referred to as a P picture), and a both direction prediction coded picture (hereinafter referred to as a B picture).
For example, in the case where one picture out of N pictures is set as an I picture, one picture out of M pictures is set as a P picture or I picture, (N×n+M)th picture constitutes an I picture, (N×n+M×m)th picture (m≠1) constitutes a P picture, pictures from (N×n+M×m+1)th picture to (N×n+M×m+M−1)th picture constitute B pictures, where n and m are integers and 1≦m≦N/M. At this time, pictures from (N×n+1)th picture to (N×n+N)th picture are referred to as a GOP (group of pictures) in summary.
FIG. 6 shows a case in which symbols N and M are defined as N=15 and M=3. In FIG. 6, the I picture is not subjected to the inter-frame prediction but only to the intra-frame conversion coding. The P picture is subjected to a prediction from the I picture immediately before the P picture or from the P picture. For example, the 6th picture in FIG. 6 is a P picture. The 6th picture is subjected to the prediction from the 3rd I picture. Further, the 9th P picture in FIG. 6 is subjected to the prediction from the 6th P picture. The B picture is subjected to the prediction from I picture of the P picture immediately before and after the B picture, for example, in FIG. 6, the 4th and 5th B pictures are subjected to the prediction both from the 3rd I picture and the 6th P picture. Consequently, the 4th and 5th picture are subjected to coding after coding of the 6th picture.
Now operation of the data compressing circuit 202 will be explained in accordance with FIG. 2. The memory circuit 301 outputs the digital video picture signals which are inputted after rearranging the signals in the coding order. In other words, as described above, for example, the first B picture is coded after the 3rd I picture in FIG. 6. Consequently, the order of pictures are rearranged. FIG. 7 shows an operation of this arrangement. A picture sequence inputted as shown in FIG. 7A is outputted in the order shown in FIG. 7B.
Further, the video signal 321 outputted from the memory circuit 301 is subjected to DCT in the direction of space axis after a difference between pictures from the prediction picture 323 outputted from the motion compensation predicting circuit 310 at the subtracter 302 to reduce the redundancy in the direction of the time axis. The converted coefficient is quantized and variable-length coded followed by being outputted via the transmission buffer 306. In the meantime, the quantized conversion coefficient is inversely quantized and is subjected to an inverse DCT. After that, the coefficient is added to the prediction picture 323 at the adder 309 and a decoded picture 322 is obtained. The decoded picture 322 is inputted to the motion compensation predicting circuit 310 for the subsequent coding of pictures.
Subsequently, an operation of the motion compensation predicting circuit 310 will be explained in accordance with FIG. 3. The motion compensation predicting circuit 310 uses two reference pictures which are stored in the frame memory 404a and the frame memory 404b to perform a motion compensation prediction of the video signal 321 outputted from the memory circuit 301 for outputting the prediction picture 323.
In the beginning, in the case where the picture 322 coded and decoded as described above is either an I picture or a P picture, this picture 322 is stored in the frame memory 404a or the frame memory 404b for coding the subsequent picture. At this time, the switcher 403 is switched so that the frame memory out of the two frame memories 404a and 404b which is renewed prior to the other in time is selected. However, when the decoded picture 322 is a B picture, writing is not performed at the frame memory 404a and the frame memory 404b. 
For example, when 1st and 2nd pictures in FIG. 7 are coded by such switching of the switcher 403, the 0th P picture and the 3rd I picture are stored in the frame memory 404a and frame memory 404b, respectively. Further, when the 6th P picture is coded and decoded, the frame memory 404a is rewritten into the decoded picture of the 6th P picture.
Consequently, when the 4th and the 5th B pictures are coded, the 6th P picture and the 3rd I picture are stored in the frame memories 404a and 404b, respectively. Further, when the 9th P picture is coded and decoded, the frame memory 404b is rewritten into the decoded picture of the 9th P picture. As a consequence, when the 7th B picture and the 8th B picture are coded, the 6th P picture and the 9th P picture are stored in the frame memories 404a and 404b, respectively.
When the video signal 321 outputted from the memory circuit 301 is inputted to the motion compensation predicting circuit 310, the motion vector detecting circuits 405a and 405b detect a motion vector on the basis of a reference picture stored in the frame memories 404a and 404b and output a motion compensation prediction picture. In other words, the video signal 321 is divided into a plurality of blocks. Then a block is selected so that the prediction distortion becomes the smallest in the reference picture with respect to each block. Then the relative position of the block is outputted as the motion block, and at the same time this block is outputted as the motion compensation prediction picture.
In the meantime, the prediction mode selector 406 selects a picture where the prediction distortion is the smallest out of two motion compensation prediction pictures outputted from the motion vector detecting circuits 405a and 405b or an average picture thereof. Then, the selected picture is outputted as a predicted picture. At this time, when the video signal 321 is not a B picture, the motion compensation prediction picture is always selected and outputted which corresponds to the reference picture which is inputted prior to the other before in time. Further, the prediction mode selector 406 selects either coding in pictures in which prediction is not performed or prediction coding by the selected prediction picture in such a manner that the selected coding has a better coding efficiency.
At this time, when the video signal 321 is an I picture, the coding in pictures is always selected. When the coding in pictures is selected, a signal representative of the coding in the picture mode is outputted as a prediction mode. In the meantime, when the prediction coding between pictures is selected, a signal representative of a selected prediction picture is outputted as a prediction mode. The switcher 407 outputs a zero signal when the prediction mode outputted from the prediction mode selector 406 is a mode of coding in pictures. If the prediction mode is not the mode of coding in pictures, the prediction mode selector 406 outputs the prediction picture.
It follows from the aforementioned fact that when the video signal 321 outputted from the memory circuit 301 is an I picture, the motion compensation predicting circuit 310 always outputs the zero signal as a prediction picture 323, the I picture is not subjected to the inter-frame prediction but to the intra-frame conversion coding. In the meantime, when the video signal outputted from the memory circuit 301 is the 6th P picture in FIG. 6, the motion compensation prediction circuit 310 performs the motion compensation prediction from the 3rd I picture in FIG. 6 and outputs the prediction picture 323. Further, when the video signal 321 outputted from the memory circuit 301 is the 4th B picture shown in FIG. 6, the motion compensation prediction circuit 310 performs the motion compensation prediction from the 3rd I picture and the 6th P picture shown in FIG. 6 and outputs the prediction picture 323.
Subsequently, an operation of the transmission buffer 306 will be explained. The transmission buffer 306 converts video data variable-length coded by the variable-length encoder 305 into a bitstream of the MPEG video signal. Here, the stream of the MPEG has a six layer structure shown in FIG. 5. Header information which is an identification code is added for a sequence layer 621, a GOP layer 622, a picture layer 623, a slice layer 624 and a block layer 626 to constitute the layer structure.
Further, the transmission buffer 306 decomposes a bitstream of a video signal and a bitstream of an audio signal into a plurality of packets respectively so that these packets are multiplexed including a synchronization signal thereby constituting a system stream of a MPEG2-PS (program stream). Here, the MPEG2-PS consists of a pack layer and a packet layer as shown in FIG. 8. Then the header information is added to the packet layer and the pack layer. In the conventional example, a system stream is constituted so that data of one GOP portion of the video data is included.
Here, the pack layer has a structure in which the packet layer is bound at the upper layer of the packet layer. Each packet layer which constitutes the pack layer is referred to as a PES packet. In addition, header information of the pack layer shown in FIG. 8 includes an identification signal of a pack and a synchronous signal which constitutes a basis of a video signal and an audio signal.
In the meantime, in the packet which constitutes the packet layer, three kinds of PES packets exist as shown in FIG. 9. Here, a second stage packet shown in FIG. 9 is a video/audio/private 1 packet wherein a code for identifying the front of the packet and time stamp information or the like (PTS and DTS) needed at the time of decoding each packet as header information are added before the packet data. However, the time stamp information PTS is a time control information of the reproduction output and is information for controlling a decoding order of data stream of each packet at the time of reproduction. Further, DTS is time control information at the start of decoding and is information for controlling the transmission order of decoding data.
The third stage packet shown in FIG. 9 is a private 2 packet where user data is written. Further, the lowest stage packet is a padding packet where all the packet data is masked with “1”. The header information in the private 2 packet and padding packet is constituted of a start code of a packet and a packet length.
As described above, the video data and audio data items are converted into a system stream of the MPEG2-PS by the transmission buffer 306 and is converted for each of the frame sectors. This information is subjected to error correction processing, and at the same time, the information is modulated to minimize the interference between codes on the disc and is recorded on the optical disc 212. At this time, for example, data amount for each of the GOP unit is set to an approximately the same amount. Then, it is apparent that the edition for each of the GOP unit can be made by distributing the data into sectors which are equal to integer times of the frame cycle.
Subsequently, an operation at the time of playback will be explained. At the time of the playback, the video information recorded on the optical disc 212 is amplified with the playback amplifier 213. After the information is restored to digital data at the demodulator 214 and the error correction decoder 215 followed by being restored as pure original video data free of data such as an address and a parity at the frame sector inverse converting circuit 216. Then, the data is inputted into the data extending circuit 217 which has a structure shown in FIG. 4. The system stream which consists of a MPEG2-PS is inputted to the transmission buffer 501.
At the transmission buffer 501, the system stream which is inputted is decomposed into a pack unit. After that, each PES packet is decomposed in accordance with the header information thereby reconstructing the bitstream of the video data and audio data which is decomposed in the PES packet unit. Further, with respect to the video data, the stream is decomposed to the block layer shown in FIG. 5 so that the block data and the motion vector data is decomposed and outputted.
The block data outputted from the transmission buffer 501 is inputted in accordance with the variable-length decoder 502 so that the variable-length data becomes a fixed length data, inversely quantized and is subjected to the inverse DCT to be outputted to the adder 506. In the meantime, the prediction data decoding circuit 505 decodes the prediction picture in accordance with the motion vector outputted from the transmission buffer 501 to be outputted to the adder 506.
In this case, the prediction data decoding circuit 505, like the motion compensation predicting circuit 310, provides a frame memory for storing the I picture and P picture data which is decoded by the adder 506. Incidentally, with respect to a method for renewing the reference picture data an explanation will be omitted because the method is the same as the case of coding the data.
The adder 506 adds the output of the prediction data decoding circuit 505 and the output of the inverse DCT circuit 504 to be outputted to the memory circuit 507. Here, at the time of coding the data, the frame is rearranged in accordance with the order of coding the data as shown in FIG. 7 with respect to the video signals which are continuous in time. Therefore, in the memory circuit 507, the data inputted in the order shown in FIG. 7B is rearranged so that the picture data continues in time and is outputted to the D/A converter 218.
Subsequently, the picture retrieval and the high speed playback thereof will be shown in the case where data with such a coding structure is recorded on the optical disc. In the case where the coding structure shown in FIG. 6 is provided, the high speed playback of the picture can be performed when the data is played back in the unit of the I picture. In this case, the track jump is performed immediately after the I picture is played back. Then, the following or the preceding GOP is accessed so that the I picture is played back there. In the case shown in FIG. 6, the high speed feeding playback and rewinding playback can be actualized by repeating such an operation.
However, since this GOP rate is a variable bit rate, it is impossible to recognize at all where the front of the following GOP is located. Consequently, the optical head is allowed to appropriately jump to locate the front of the GOP. Thus, it is impossible to determine which track should be accessed.
In addition, the I picture has a large amount of data. Thus, when only the I picture is played back in a continuous manner, like a special playback, the picture cannot be played back at a frequency of 30 Hz like a normal animated picture because of a limit on the reading speed from the disc. Even when the optical head jumps after the completion of the I picture playback, the intermission for the renewal to the following I picture becomes longer so that the operation lacks in smoothness.
The conventional digital video signal record and playback device, is constituted in the aforementioned manner. In the case where a high speed playback is performed at several times speed by using the I picture and the P picture, the I picture data and the P picture data is read after the front of the GOP is detected from bitstreams which are recorded on a recording medium or the like such as an optical disc or the like. Consequently, in the case where the data amount of the I picture and the P picture become very large, or in the case where it takes much time to search the front of the GOP, time for reading the data from the recording medium becomes insufficient. Thus there arises a problem in that the data all the I picture and the P picture cannot be read so that the high speed playback cannot be realized.
In the conventional digital video signal record and playback device, it takes much time to input I picture data which has a large amount of data even when the high speed playback is performed only by using the I picture. Consequently the special playback which surpasses tens of times cannot be realized. In this case, a higher speed special playback can be realized by playing back one I picture for several GOP. There is a problem in that the interval for the renewal of played back picture will be prolonged so that the content of the picture will become vague.
Since the conventional video signal record and playback device is coded as described above, only the I picture having a large amount of data is decoded at the time of the skip search (watching data through a rapid playback). Consequently, the optical head is allowed to jump without playing back data sufficient for the decoding. Otherwise, when a sufficient amount of data is played back, the time for the playback of data is long, the destination to which the GOP is to jump must be set to a considerably far place causing a problem that the number of scenes outputted to the screen becomes few.
In addition, since the sector address of the following GOP cannot be recognized because of the variable rate, it is not verified whether or not the front of the GOP is located at the track to which the jump is made. Consequently, there arises a problem in that a plurality of disc rotation are required to locate the front of the GOP at the track of destination and the number of scenes which are outputted to the screen becomes much fewer at the time of the special playback. Further, there arises a problem in that if the sector address can be recognized, no means is available for judging to what extent data can be played back for the optical head jump with the result that no judgement can be made without passing through the video decoder, and the efficiency at which the optical head jumps is lowered.
As other conventional digital video signal record and playback devices, some devices are disclosed in, for example, Japanese Patent Application Laid-Open No. HEI 6-98314 (1994), Japanese Patent Application Laid-Open No. HEI 6-78289 (1994) and the like. One example is shown in FIG. 10. In FIG. 10, reference numeral 775 denotes a video signal generator such as a camera, a VTR or the like, 776 an audio signal generator such as a microphone, a VTR or the like, 762 a video signal encoder, 763 an audio signal encoder, 777 a system layer bitstream generator, 778 an error correction coder, 779 a digital modulator, 780 an optical disc, 756 a playback amplifier, 786 a detector, 781 a digital demodulator, 758 an error corrector, 759 a system stream processor, 782 a video signal decoder. 782 an audio signal decoder 784 a monitor and 785 a speaker.
Currently, optical discs generally used have a diameter of 120 mm. These optical discs are normally capable of recording 600 M byte or more data. Quite recently, these optical discs are capable of recording video signal and an audio signal for 74 minutes at a data rate of about 1.2 Mbps. At the time of data recording, a video signal is inputted to the video signal encoder 762 from the video signal generator 775 for encoding the video signal. From the audio signal generator 776, the audio signal is inputted to the audio signal encoder 763 for encoding the audio signal. The process for multiplexing the header or the like to these two encoded signals is carried out by the system layer bitstream generator 777. After the error correction code is appended by the error correction coder 778, the error correction signal is digitally modulated with a digital modulator 779 thereby generating a bitstream for recording. This bitstream creates a mother disc with a recording means (not shown), and the content of the mother disc is copied to the optical disc 780 with the result that a commercially available video software disc is prepared.
In a playback device for users, a signal obtained from the video software disc by the optical disc is amplified with the playback amplifier 756 to input a playback signal to the detector 786. After this playback signal is detected with the detector 786, the digital demodulator 781 digitally demodulates the signal to correct errors with an error corrector 758. After this, the video signal area is extracted from the signal which has been error corrected, and this extracted data is decoded at the video signal decoder 782 and outputted together with the audio signal decoded by the audio signal decoder 783 to the monitor 784 and the speaker 785 respectively.
A typical method for coding this video signal is an MPEG 1 and an MPEG 2 referred to as an MPEG (Moving Picture Experts Group) method which is an international standard coding method. A concrete example of coding method will be explained with respect to an example of MPEG 2.
FIG. 11 shows a block diagram of an video signal coding part in a conventional digital signal record and playback device for explaining the MPEG2 coding method. FIG. 12 is a block diagram of an video signal decoding unit in a conventional digital signal record and playback device for explaining a decoding method. Further, FIG. 13 is a view showing a concept of the mobile picture processing for the video signal coding in the conventional digital signal record and playback device for explaining the grouping of mobile pictures according to the coding method of the MPEG 2. Referring to FIG. 13, IBBPBBP designates - - - , I an I picture, B a B picture and P a P picture. For example, in FIG. 13A, mobile pictures from I to the one immediately before the appearance of another I are grouped in a definite number of frames. The number of frames of the pictures which constitute this group is normally 15 frames in many cases. However, the number is not limited to any specific number.
The GOP, a group of pictures which constitutes this group includes at least one frame of I picture which can be decoded completely in one frame. The GOP also includes a P picture coded through the motion compensation prediction by one direction prediction of the time system on the basis of the I picture and a B picture coded by both direction prediction of the time system on the basis of the I picture and the P picture. Incidentally, the arrows in FIGS. 13A and 13B represent prediction relations.
In other words, the B picture can be coded and decoded only after the I picture and the P picture are prepared. The initial P picture in the GOP can be coded and decoded after the I picture before the P picture is prepared. The second P picture and P picture after that can be coded and decoded when the P picture immediately before the P picture is prepared. Consequently, in the absence of the I picture, either the P or B pictures cannot be coded and decoded.
Referring to FIG. 11, reference numeral 787 denotes a picture rearranger, 788 a scan converter, 789 an encoder buffer, 790 a mode determiner, 702 a motion vector detector, 706 a subtracter, and 708 a DCT circuit which has a field memory, a frame memory, and DCT calculator. Reference numeral 710 denotes a quantizer, 714 an inverse quantizer, 716 an inverse DCT circuit, 718 an adder, 720 an image memory, 722 a rate controller and 726 a variable-length encoder.
Referring to FIG. 12, reference numeral 733 denotes a variable-length decoder, 736 an inverse DCT circuit, 737 an image memory, 788 an adder, 739 an inverse scan converter. Incidentally, the motion vector detector 702 and the mode determiner 790 combines together to represent a motion vector detecting unit.
Subsequently, on the basis of FIGS. 11 though 13, an operation of a digital video signal record and playback device will be explained. Referring to FIG. 11, the picture rearranger 787 rearranges pictures for coding in an order shown in FIG. 13. Then the scan converter 788 converts the scan from the raster scan to the block scan. This picture rearrangement and the conversion processing from the raster scan to the block scan are generally referred to as preprocessing. The picture rearranger 787 and the scan converter 788 are generally referred to as preprocessor. The inputted picture data is subjected to block scan in the order of encoding. When the picture is an I picture, the picture passes through the subtracter 706. When the picture is a P picture or a B picture, the picture is subtracted with the reference picture and the subtracter 706.
At this time, the motion vector detector 702 determines the motion direction and the notion quantity (the input of the original picture to this motion vector detector 702 may be a picture after the picture rearrangement or a picture after the block scan as an original picture, but the circuit size is smaller in the latter case. Further, the reference picture must be inputted from the image memory 720 but the reference arrow in the drawing is omitted) with the result that a signal in the area in consideration of the portion of the direction and quantity from the image memory 720 may be read. At this time, the mode determiner 790 determines whether both direction prediction is used or a one direction prediction may be used.
The substraction with the reference screen in consideration of the motion vector is performed at the subtracter 706. Even pictures with a small electric power are constituted so that the coding efficiency is heightened. The output from the subtracter 706 is collected either in a unit of field or in a unit of frame at the DCT circuit 708 to be subjected to a DCT process and converted into data in a frequency component. This data is inputted to the quantizer 710 where the weight is different for each of the frequency. The data is scanned in a zigzag manner in two dimensions over low frequency components and high frequency components to be subjected to a run length coding and a Huffman coding.
This data which has been subjected to the run length coding and Huffman coding is controlled for variable-length coding so that a quantizing table is scaled by using the rate controller 722 to allow the data to agree with a target code quantity. The data that has been subjected to variable-length coding is normally outputted via the encoder buffer 789. The quantized data is brought back to the inverse quantizer 714 to be brought back to an original picture space data by the inverse DCT circuit 716 with the result that data which is the same as the decoded data is obtained by the adder 718 by adding the original picture space data to the data referenced by the subtracter 706.
FIG. 12 shows a schematic block structure of a decoder. The variable-length decoder 733 decodes picture data including header information such as the motion vector, the coding mode, the picture mode or the like. After this decoded data is quantized, the inverse DCT circuit 736 performs the inverse DCT calculation (incidentally, in FIG. 12, the inverse quantizer located in the front stage of the inverse DCT circuit 736 is omitted). By referring to the picture data from the image memory 737 in consideration of the motion vector, the motion compensation prediction is decoded by adding the picture data that has been referred to with the data after the inverse DCT by the adder 738. This data is converted into a raster scan with the inverse scan converter 739 to obtain and output an interlace picture.
Further, in accordance with the variable transmission rate disc system introduced in “the variable transmission rate disc system and the code quantity control method” in a publication of Mr. Sugiyama et al, at the 1994 annual meeting of the Television Society, a proposal is made on a higher quality digital video signal encoding method. This is a method in which an encoding rate is fixed with one program (for example, a first set) so that each GOP is set at a rate depending on the difficulty of the design and encoded. FIG. 14 is a block diagram showing a video signal coding unit in a conventional digital signal record and playback device. In FIG. 14, reference numeral 791 denotes a motion compensation predictor, 792 a code amount memory, 793 a GOP rate setting unit, 794 a code amount assigning unit, 795 a subtracter, and 796 a code amount counter and 797 a switch. The GOP rate setting unit 793 shown in FIG. 14 is set to change the setting of the quantizing value according to the difficulty of the design pattern. In other words, while the switch 797 is connected to the virtual coding side, the output of the variable-length encoder 726 is inputted to the code amount counter 796 so that the code amount counter 796 counts the code amount to be stored in the code amount memory 792.
The GOP rate setting unit 793 determines the virtual code amount in the whole one program on the basis of the code amount stored in this code amount memory 792 to set and calculate the optimal encoding rate in each GOP. The code assignment at this time is calculated from the code amount assigning unit 794 for the preparation of the actual encoding. When the switch 797 is connected to the actual coding side, the code amount assignment amount and the value of the code amount counter 796 are compared so that the switch 797 is operated to control the quantizer 710 on the basis of the actual code amount. In this manner, a small code amount is assigned to an easy design and a large code is assigned to a difficult amount so that the coding difficulty that gradually changes in the program is absorbed. As a consequence, it has been reported that the picture quality of what is recorded at a rate of 3 Mbps by using this method is approximately the same as the picture quality of what is coded at a rate of 6 Mbps.
In consideration of the possibility of the skip search in the digital video signal record and playback device using an optical disc, when the I picture and the P picture are played back for fast rewinding even when the front of the GOP can be accessed at a high speed, the P picture is located at an appropriate position in the GOP so that there arises a need of operating the optical head while searching data on the bitstream. However, such a control cannot be made in time because of the time constant of a servo such as an actuator or the like. One GOP normally includes 15 frames of pictures, and in NTSC scanning method, 0.5 second is available for finding the front of the GOP. However, in order to detect the front of a certain GOP, the bitstream requires the reading of ½ or more for reading ⅓ picture at a frame rate even when an attempt is made to read the I picture or the P picture at the time of the skip search with the result that the reading speed has to be set to 2.5 times faster or even faster than the normal speed when the head movement time is set to 200 milliseconds. This exceeds the response limit of the actuator. In a normal playback method, the skip search is substantially impossible to carry out.
In accordance with the conventional digital video signal record and playback device, the signal is coded in this manner. Thus, when an attempt is made to perform the skip search like a video tape recorder, a perfect playback picture cannot be obtained in the case where the data is played back which does not allow obtaining a complete original picture from one picture data item like the B picture. Particularly, in the skip search, jerkiness (unnatural movement) is generated with respect to the output processing in the unit of frame. When a variable rate recording is performed with a good playback picture quality, there arises a problem in that the difficulty of accessing the front of the GOP itself increases since the position of the front address of the GOP changes, with the result that a space is formed in a disc area due to disuniform unit of the GOP.